View CCD5061_938142.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

preliminary data sheet CCD5061 6k x 128 element tdi ? time , delay and integration sensor gener a l d escription the ccd50 6 1 is a 61 44 pixel x 128 l i ne, high sp eed t d i sen s o r . t he a c tive im a g ing area is organ ized as 61 44 vertical colu mns and 1 28 h o ri zontal tdi ro ws. t he a r ray is set up f o r bi -dire c tional op eration. the r e are identical outp u t regi sters and a m plifiers o n both the top and the b o ttom of the a rray. the output s to be u s e d (either to p o r bottom) are use r -sel ecta b l e and controlled by the ve rtical cl ock pha sing. in a d d i tion, the expo su re level ca n be controll ed by redu cin g the numbe r of tdi rows from 128 to 64, 32, 1 6 , 8 o r 4. this i s also use r - sele ctabl e an d is accom p li she d by supp lying the appropri a te phasi n g for the vertical clo c k s wit h in eac h se ct io n. for in st a n ce, if 64 lin es of t d i were req u ired, th e ve rtical clo c ks for lin es 65 -1 28 would be co nn ecte d to a high potential, which woul d drai n these unu sed ro ws out to t he op po site side (unu se d) of the array to be dumpe d in the drain. with four output s, ea ch ru nnin g at 20mhz, the ccd5 061 ca n provide a total data rate of 8 0 mhz ena bli ng the ccd t o run at better th a n 12k hz li n e rate. utili zing fairchild ima g ing propri e tary buri ed ch anne l ccd p r o c e ss, the ccd506 1 a c hieves con s i s tent, su perio r tdi pe rforma nce. fe a t ures ? 614 4 p i xels p e r lin e ? 128 lin es o f integ r atio n ? 8.75 m x 8.75 m p i xel size ? # o f t d i stag e s select ab le fr o m 128, 64, 32 , 16, 8, 4 ? bi-dire c t iona l tdi li ne s h ifti ng (s hif t u p or do w n ) ? 4 outpu ts ?e ac h c a p a b le of 2 0 m hz da ta rate? 80mhz t o tal data rate ? 100% fill factor ? on-c hip bi nn i ng c a p a b il ity the four h o ri zontal o u t put regi sters utili ze 4- pha se clo c king. spe c ial desi gn te chni que s have bee n implemente d to maximize ch arg e transfe r efficiency espe cially at low light levels. th e output am pl ifier is a 3 - stage sou r ce follower co nfigu r ati on. this all o ws maximum scale facto r (charg e to vol t age conve r si on ) a nd maximum band width. the ccd506 1 is hou se d in a cu stom 176 pin (100 mil grid ) cerami c pga pa ckag e. it has a n ar co ated win d o w . fu nc tional d escr i ption the followi ng function al element s are illustrated in the block di agram: image sens ing elements: t h es e a r e element s of a line of 6 1 4 4 imag e sen s ors sep a rate d by cha nnel stop s an d covere d by a pa ssivatio n layer. in cid ent photo n s pass through a transparent pol ycrystalline si licon gate stru cture creatin g el ectro n h o le pairs. the re sultin g photoel ectron s are coll ecte d in the photo s ite s du ring the i n tegratio n pe riod. the am ount of cha r ge accumul a ted in each photo s ite is a linear fun c tio n of the localize d incid ent illumi nation inte nsi t y and integration perio d. the active i m aging a r ea is sepa rated fro m the four h o ri zontal o u tput regi sters by 21 isolatio n rows. th ese i s olatio n rows a r e covered by a metal lig htshiel d to p r otect them while charg e tra n sf ers to the o u tput regi sters. both the active imaging a r ea and the isolatio n region utili ze 3 - pha se clo cki ng. trans f er ga tes : t h is gate is a structure adja c ent to the row of image sensor element s. the cha r ge pa ckets a c cum u l a ted in the photosites are tra n sferred in pa rallel via the transfer gate to the tran spo r t shift 1801 mccarth y blvd., milpita s ca 95035; (8 00) 3 25-6975; fa x (40 8 ) 435- 7352; ww w . f a irchildimaging.com page 1 o f 17
preliminary data sheet CCD5061 6k x 128 element tdi ? time , delay and integration sensor regi sters whe never the tra n sfer gate vol t age goe s high. shift registers: t he ve rtical shift re giste r is 3 - ph ase an d the ho ri zont al shift regi ster i s 4-ph ase. time dela y and integ r ati on: this func tion is accom p lished by sca nning the i m age scene acro ss the array at the sa me rate a s the vertical shift regi ster moves th e si gna l cha r ge. thi s results in an effective increase in the integrat ion time. output am plifier: the ccd506 1 is desi gne d for either uni-dire c tional fo r bi- dire ctional o peratio n. there are four identical outp u t regi sters and a m plifiers o n both the t op and bottom o f the array. there are th ree - sta ge source f o llower am pl ifiers with a re set mosfet tied to the input gate. cha r ge pa ckets are clocked to a pre - cha r ge d cap a citor who s e potential ch ange s linearly in resp on se to the numb e r of electron s d e li vered. thi s p o tential i s ap plied to the inp u t gate of an nmos am plifier prod uci ng a sign al at the output v out pin. the cap a cit o r is re set wi t h r to a pre - cha r ge level prio r to the a rrival of the next cha r ge pa cket exce pt whe n ho ri zo ntally binnin g . it is re set by use of the reset mosfet. the outp u t a m plifier d r ain is tied to v dd. the sou r ce i s con n e c ted to an exte rnal l oad resi sto r to ground. th e source con s titutes the video out put from the device. definitio n of terms charg e -cou pled dev i c e : a ch arge - coupled dev ice i s a monolithi c silicon stru cture in whi c h discrete pa cket s of electron ch arge are tran spo r ted from positio n to p o s ition by se q uential clo cki ng of an array of gates. isolation ro w s : the r e are 21 i s ol ation rows bet wee n the image area an d the hori z ontal shift registe r . t hese no n-im a g ing rows are u s ed a s buffer ro ws to eli m inate cro s stalk to t he hori z o n tal shift regi ster. d y namic range: t he ratio of satu ration output voltag e to rms n o ise in the dark. the p e a k -to - pea k rand om noise i s 4 - 6 t i mes the rms noi se output. rms nois e equiv a lent exposure : the exposure lev e l that give s an output signal equal to the rms n o ise le vel at the out put in the dark. satura tion exposur e: the minimum exposure le vel that pro duces an o u tput sign al corre s po ndin g to the maxi mum photo s ite ch arge cap a cit y . exposure is equal to the prod uct of l i ght intensity and integratio n time. charg e tr a n sfer efficie n c y : perce n tage of valid cha r g e information that is t r an sfe rre d betwe en e a c h su ccessi ve stage of the transpo rt regi ster. responsiv it y : the out put si gnal v o ltage per unit of exposure. photo-re sp onse non-uniformity : the differen c e of the re spo n se levels b e twee n the most an d the least sen s itive reg i on s unde r unif o rm ill umin ation (excl uding blemished element s) e x presse d a s a percenta ge of the average respon se. dark signal: the output sign al cau s e d by thermally ge nerate d el ect r on s. da rk sign al is a lin ear fu n c tion of inte gration time an d an expone ntial functio n of chi p temperature. integration time: the time i n terval betwe en the falling ed g e s of a n y two su ccessive t r ansfe r pul se s is the i n tegration time sh own in the timin g diag ram. the integratio n time is the time allowed for the photo s ites to colle ct ch arg e . pixel: picture eleme n t or sen s o r ele m ent, also calle d ph otoeleme n t or photosite. 1801 mccarth y blvd., milpita s ca 95035; (8 00) 3 25-6975; fa x (40 8 ) 435- 7352; ww w . f a irchildimaging.com page 2 o f 17
preliminary data sheet CCD5061 6k x 128 element tdi ? time , delay and integration sensor 6k x 128 tdi imaging area block diagr a m h1 h2 h3 h4 v out1 v1 v2 v3 v out2 v out3 v out4 v out1 vo u t 2 v out3 v out4 21 isolation rows horizontal registers 21 isolation rows horizontal registers 1801 mccarth y blvd., milpita s ca 95035; (8 00) 3 25-6975; fa x (40 8 ) 435- 7352; ww w . f a irchildimaging.com page 3 o f 17
preliminary data sheet CCD5061 6k x 128 element tdi ? time , delay and integration sensor dev i ce architec ture arra y siz e 614 4 pi xels per line; 12 8 li nes of integrati on t d i pixel siz e 8.75m x 8.7 5 m image f o rmat 53.76 x 1.1 2 mm 2 numb er of outputs 8 4 t op, 4 botto m pixel output r a te 80mhz 20mhz x 4 outputs number of vertical clocks 3 numb er of isolation r o w s 21 top, 21 b o ttom number of horizontal clocks 4 pixel r a te per output 20mhz performan c e specificatio ns s y m b o l p a r a mete r m i n . no min a l m a x . un its/rema rk s v sat saturatio n volt a g e 1 . 5 v q sa t saturatio n ch a r ge 350 450 ke- at 12khz vlin lin earit y 1% 5% 10% to 90 % f u ll w e ll sf s c a l e f a c t o r 2 . 5 3 . 3 v / e - d r d y n a m i c r a n g e 1 0 , 0 0 0 hct e horizo ntal ct e .9999 8 0.999 99 0 per t r ansfer vct e vertical ct e .9998 0.999 90 per t r ansfer n e r e a d nois e 4 0 5 0 e - r m s p r n u p h o t o r e s po nse non-u n iformit y 5 2 0 % d e v i c e f l atnes s 3 0 m 1801 mccarth y blvd., milpita s ca 95035; (8 00) 3 25-6975; fa x (40 8 ) 435- 7352; ww w . f a irchildimaging.com page 4 o f 17
preliminary data sheet CCD5061 6k x 128 element tdi ? time , delay and integration sensor test con d i t ions all testing p e rform e d at 25oc (nomin al) with hori z o n tal clo ck fre q u ency of 20m hz per output a n d vertical cl o ck f r eq uen cy of 12khz. cc d h a ndl ing prec a u tio n s to prevent esd damage by their very nature, ccds a r e very se nsitive to electro-static discha rge (e sd) d a ma ge. speci a l esd-control equipm ent a nd p e rson nel trainin g are m andat o r y, particularl y when in st alling o r r e mo ving th e c c d fr o m a c a mer a s y s t e m . se e fairchild imaging applicat ion note ?pre vention of esd dama g e in ccd image sen s ors? for details. key points: use esd-safe wo rkben ch su rfaces. cove r metallic workbench surf aces with esd-safe grou nde d m a ts. rem o ve non-es d-safe material s (pa per, tool s wit h plasti c ha n d les, etc.) from work are a . use wri s t st rap s or eq ui valent (~1 m ? to grou nd ), esd-safe lab coat or eq uivalent (buttone d?n o t open ), an d esd-safe glove s or finger c o ts . tes t wris t s t rap before handli ng ccds. relative hum idity must be 40% min.; >50% recomme nde d. use ioni zing air blo w e r s; t y pe: ac (not pulsed dc), bala n ce d~ r 20v ~ max., d~ r 10v ~ recomme nde d. performance spe c a t work area: voltage decay fro m 1000v to 1 00v in <10 se con d s. measure this pe riodi cal l y; air ionizers re qui re mainte nan ce. allow devi c e s to slo w ly discha rge i n the ionized air stream when removing d e vice s from their 1st-level co ntainer, a n d whe n removing dev ic es from tes t s o ck et s . the re ceivin g socket a nd a s soci ated ci rcuitry must be ad eq uately grou nd ed. store ccds with all pins shorted tog e th er by sho r ting bars, cond uctiv e foam, o r the equivalent. esd damag e invalidates th e warra n ty. 1801 mccarth y blvd., milpita s ca 95035; (8 00) 3 25-6975; fa x (40 8 ) 435- 7352; ww w . f a irchildimaging.com page 5 o f 17
preliminary data sheet CCD5061 6k x 128 element tdi ? time , delay and integration sensor CCD5061 output amplifier vo ltages & ex ternal load sy m b o l p a r a m e t e r rang e u n i t rem a r k s m i n n o m m a x vdd amplifier dc supply 23 v i dd + 1 5ma /pin, depe nding o n rout. see note 1 vrd re set drain 16 v see note 1 vofd overflow drai n 16 v see note 2 vsrc curre n t sou r ce (?sign al gnd ?) from amplifie r 1 st & 2 nd st age s 2 . 5 v i src ? -1.5ma /pin vgt bias voltage, amplifier 1 st & 2 nd - s ta ge c ons ta n t -c ur r e n t - sou r ce fets 4 v i gt << 1na /pin vog output gate dc bi as -4 v i og << 1na /pin v s s s u b s t r a t e [ g r o u n d ] 0 v rout output loa d on ea ch vout pin to vss 0 . 7 5 1 . 0 k ? at 20mhz/o utput, use 1.0k ? total of external load re si stor + pre a mp input imped a n ce note 1: whe never v d d>+12v, vrd mu st be b i ase d at not less than 12v less than vdd: vrd (v dd -1 2v) for all vd d> +1 2v a zene r diod e circuit is re comm end ed to ensure th at this condition is always met. if this con d ition is not met, even momenta r il y, t hen perm anent da mag e to the amp lifier may result. note 2: (vrd-2v ) preliminary data sheet CCD5061 6k x 128 element tdi ? time , delay and integration sensor CCD5061 clock voltages sy m b o l p a r a m e t e r rang e u n i t rem a r k s m i n n o m m a x v1 v2 v3 slow vertical shift regi ster clo ck clo c k - hi gh clo c k - lo w v-dump +18 0 +15 v v v v1-hs v2-hs v3-hs fast v e rt ic al shif t regi st er clo c k s clo c k - hi gh clo c k - lo w v-dump +15 0 +15 v v v h1 hori zo nt al shi f t regist er clo ck, and v h t r a n sf er clo ck trilevel (v h tran sfer) clo c k-hi gh (transport only ) clo c k-lo w (t ran s po rt only) h-d u mp +5 0 -5 +3 v v v v note 1 note 1 h2 h3 h4 hori zo nt al shi f t regist er clo ck clo c k - hi gh clo c k - lo w h-d u mp 0 -5 +3 v v v note 1 note 1 note 1 og clo c ked outp u t gate clo c k - hi gh clo c k - lo w h-d u mp 1 -5 +3 v v v note 1 note 1 r res e t gate clock clo c k - hi gh clo c k - lo w +15 +4 v v note 1: may requi re i ndividually tuned voltage s fo r optimum p e rform a n c e e s pe cially at hi gh sp eed. 1801 mccarth y blvd., milpita s ca 95035; (8 00) 3 25-6975; fa x (40 8 ) 435- 7352; ww w . f a irchildimaging.com page 7 o f 17
preliminary data sheet CCD5061 6k x 128 element tdi ? time , delay and integration sensor CCD5061 clock capacitance sy m b o l p a r a m e t e r rang e unit remar ks min nom max photosite rows: v1, v2, v3: capa citan c e per ro w v1 to vss 16 pf v1 to v2 19 pf v1 to v3 18 pf v2 to vss 24 pf v2 to v3 22 pf v3 to vss 22 pf isolation a nd high-sp eed ro ws: capa citan c e pe r ro w v1 to vss 20 pf v1 to v2 19 pf v1 to v3 18 pf v2 to vss 30 pf v2 to v1 (see above ) v2 to v3 22 pf v3 to vss 31 pf v3 to v1 (see above ) v3 to v2 (see above ) hori zo ntal tra n sp ort gate capa cita n c e p e r 153 6-elem ent output se ction h 1 9 0 1 1 0 p f includi n g inte r- pha se coupli ng cap a cita nce (typical 50 pf) h 2 9 0 1 1 0 p f h 3 9 0 1 1 0 p f h 4 1 1 0 1 3 0 p f 1801 mccarth y blvd., milpita s ca 95035; (8 00) 3 25-6975; fa x (40 8 ) 435- 7352; ww w . f a irchildimaging.com page 8 o f 17
preliminary data sheet CCD5061 6k x 128 element tdi ? time , delay and integration sensor s p ect r al q u an t u m e f f i ci en cy 0% 5% 10 % 15 % 20 % 25 % 30 % 35 % 40 % 45 % 50 % 40 0 4 50 5 0 0 5 5 0 60 0 6 50 7 0 0 7 5 0 8 0 0 8 50 90 0 9 5 0 10 00 (n m ) quantum efficiency t y pical qe curve for CCD5061 1801 mccarth y blvd., milpita s ca 95035; (8 00) 3 25-6975; fa x (40 8 ) 435- 7352; ww w . f a irchildimaging.com page 9 o f 17
preliminary data sheet 1801 mccarth y blvd., milpita s ca 95035; (8 00) 3 25-6975; fa x (40 8 ) 435- 7352; ww w . f a irchildimaging.com page 10 of 17 CCD5061 6k x 128 element tdi ? time , delay and integration sensor clo ck timi ng overview (1x1 full-re sol u tion mode ) ( 12khz ) -1 83 s v1 v2 v3 vhs1 vhs2 vhs3 h1 t r ilevel high h1 h2 h3 h4 fog ( og) rg ( r) vout pixel #0001 (line #n+1) pixel #1536 (line #n+1) pixel #1536 (line #n) pixel #0001 (line #n) (see detail view ) 76. 8 s at 20m pixel/sec 5 s ( 7 s pr eferred) note: for 12k- t di , to m a xi m i ze full well ( q sat ) at (20m hz h-clocks, 12khz v- clocks) , use: f o r v1 & v2: t ri se (0 %~9 0 % ) = t fa l l ( 100%~10%) = 4 s f o r v3:??. t ri se (0 %~9 0 % ) = t fa l l ( 100%~10%) = 7 s
preliminary data sheet 1801 mccarth y blvd., milpita s ca 95035; (8 00) 3 25-6975; fa x (40 8 ) 435- 7352; ww w . f a irchildimaging.com tdi ? time , delay and integration sensor page 11 of 17 CCD5061 6k x 128 element vertical -to-ho rizo ntal clo ck timing (1x1 full-re sol u tion mode) vhs1 vhs2 vhs3 h1 trilevel hi g h h1 h1- t r ilevel- high m u st star t within this ti m e p er i o d h2 h3 h4 fog ( og) o p tional ? fo g ma y be clocked here rg ( r) vout 0.000 s 4 hor iz. over s can cells ( 16 r eco m m ended) 0. 7 s each ( 1. 0 s pref er red) pixel #1536 (line #n) p ixel #1 ( line #n+ 1 )
preliminary data sheet 1801 mccarth y blvd., milpita s ca 95035; (8 00) 3 25-6975; fa x (40 8 ) 435- 7352; ww w . f a irchildimaging.com page 12 of 17 CCD5061 6k x 128 element tdi ? time , delay and integration sensor 4-ph ase ho ri zontal clo ck timing (1x1 f u ll-resolution mode ) 50ns @ 20m hz 6. 25ns ty p @ 20mhz h1 h3 h4 in dar k in light v v zr h-o v ers can # 3 h-o v ers can # 2 h-o v ers can # 1 zr = zero ref e rence vv = valid video pixel #1535 pixel #1536
preliminary data sheet CCD5061 6k x 128 element tdi ? time , delay and integration sensor CCD5061 pin name and descri p tion pin name signal description remarks vtg-t vertical t r an sfer g a te ? top v1hs-t high spe ed vertical shift phase 1 gate s?t op, ro ws 1-3 v2hs-t high spe ed vertical shift phase 2 gate s?t op, ro ws1-3 v3hs-t high spe ed vertical shift phase 3 gate s?t op, ro ws 1-3 v3x-t vertical regi ster pha s e 3 ? top, isolati on ro ws 1 - 1 8 v1x-t vertical regi ster pha s e 1 ? top, isolati on ro ws 1 - 1 8 v2x-t vertical regi ster pha s e 2 ? top, isolati on ro ws 1 - 1 8 vsw12b-d vertical regi ster pha s e 3 gate - pixel row 1 t u rn off for t d i-128 d o w n v1a-t vertical regi ster pha s e 1 gate - pixel rows 1-4 v2a-t vertical regi ster pha s e 2 gate - pixel rows 1-4 v3a-t vertical regi ster pha s e 3 gate - pixel rows 1-4 vsw4-u vertical regi ster pha s e 3 gate - pixel rows 5 turn off for t d i-4 up v1c-t vertical regi ster pha s e 1 gate - pixel rows 5-8 v2c-t vertical regi ster pha s e 2 gate - pixel rows 5-8 v3c-t vertical regi ster pha s e 3 gate - pixel rows 6-8 vsw8-u vertical regi ster pha s e 3 gate - pixel row 9 turn off for t d i-8 up v1d-t vertical regi ster pha s e 1 gate - pixel rows 9-1 6 v2d-t vertical regi ster pha s e 2 gate - pixel rows 9-1 6 v3d-t vertical regi ster pha s e 3 gate - pixel rows 10-16 vsw16 -u vertical regi ster pha s e 3 gate - pixel row 17 turn off for t d i-16 u p v1e-t vertical regi ster pha s e 1 gate - pixel rows 17-32 v2e-t vertical regi ster pha s e 2 gate - pixel rows 17-32 v3e-t vertical regi ster pha s e 3 gate - pixel rows 18-32 vsw32 -u vertical regi ster pha s e 3 gate - pixel row 33 turn off for t d i-32 u p v1f-t vertical regi ster pha s e 1 gate - pixel rows 33-64 v2f-t vertical regi ster pha s e 2 gate - pixel rows 33-64 v3f-t vertical regi ster pha s e 3 gate - pixel rows 34-64 vsw64 vertical regi ster pha s e 3 gate - pixel row 65 turn off for tdi-6 4 up/do w n v1f-b vertical regi ster pha s e 1 gate - pixel rows 65-96 1801 mccarth y blvd., milpita s ca 95035; (8 00) 3 25-6975; fa x (40 8 ) 435- 7352; ww w . f a irchildimaging.com page 13 of 17
preliminary data sheet CCD5061 6k x 128 element tdi ? time , delay and integration sensor pin name signal description remarks v2f-b vertical regi ster pha s e 2 gate - pixel rows 65-96 v3f-b vertical regi ster pha s e 3 gate - pixel rows 66-96 vsw32 -d vertical regi ster pha s e 3 gate - pixel row 97 t u rn off for t d i - 32 do w n v1e-b vertical regi ster pha s e 1 gate - pixel rows 97-112 v2e-b vertical regi ster pha s e 2 gate - pixel rows 97-112 v3e-b vertical regi ster pha s e 3 gate - pixel rows 98-112 vsw16 -d vertical regi ster pha s e 3 gate - pixel row 11 3 t u rn off for t d i - 16 do w n v1d-b vertical regi ster pha s e 1 gate - pixel rows 113 -12 0 v2d-b vertical regi ster pha s e 2 gate - pixel rows 113 -12 0 v3d-b vertical regi ster pha s e 3 gate - pixel rows 114 -12 0 vsw8-d vertical regi ster pha s e 3 gate - pixel row 12 1 turn off for t d i-8 do wn v1c-b vertical regi ster pha s e 1 gate - pixel rows 121 -12 4 v2c-b vertical regi ster pha s e 2 gate - pixel rows 121 -12 4 v3c-b vertical regi ster pha s e 3 gate - pixel rows 122 -12 4 vsw4-d vertical regi ster pha s e 3 gate - pixel row 12 5 turn off for t d i-4 do wn v1a-b vertical regi ster pha s e 1 gate - pixel rows 125 -12 8 v2a-b vertical regi ster pha s e 2 gate - pixel rows 125 -12 8 v3a-b vertical regi ster pha s e 3 gate - pixel rows 125 -12 8 vsw128 -u vertical regi ster pha s e 3 gate - isolation ro w 1 turn off for t d i-12 8 up v1x-b vertical reg i st er phase 1 ga te?bottom is olation ro w s 1 - 18 v2x-b vertical reg i st er phase 2 ga te - bottom iso l ation ro w s 1- 18 v3x-b vertical reg i st er phase 3 ga te - bottom iso l ation ro w s 1- 18 v1hs-b high speed vertical shift ph ase 1 gates ? bottom ro w s 1-3 v2hs-b high speed vertical shift ph ase 2 gates ? bottom ro w s 1-3 v3hs-b high speed vertical shift ph ase 3 gates ? bottom ro w s 1-3 vtg-b vertic al trans f er gate - bottom 1801 mccarth y blvd., milpita s ca 95035; (8 00) 3 25-6975; fa x (40 8 ) 435- 7352; ww w . f a irchildimaging.com page 14 of 17
preliminary data sheet CCD5061 6k x 128 element tdi ? time , delay and integration sensor pinout diagram a b c d 1 v s s v s s v s s v s s 1 2 v 1 f - t v 2 f - t v s w 6 4 v 3 f - b 2 3 v 1 e - t v 2 e - t v s w 3 2 - d v 3 e - b 3 4 v 1 d - t v 2 d - t v s w 1 6 - d v 3 d - b 4 5 v 1 c - t v 2 c - t v s w 8 - d v 3 c - b 5 6 v 1 a - t v 2 a - t v s w 4 - d v 3 a - b 6 7 v 1 h s - t v 2 h s - t v s w 1 2 8 - u v 3 x - b 7 8 v t g - t v 3 h s - t v 1 x - b v 2 x - b 8 9 og-t 1 , t2 r-t 1 , t2 r-b1, b2 og-b1, b2 9 10 n / c v s s n / c a g n d 10 11 n / c n / c n / c n / c 11 12 a g n d n / c v s s n / c 12 13 h2- t 1, t2 h3- t 1, t2 h4-b 1, b2 h1-b 1, b2 13 14 v s r c - 1 v s s v r d - b 1 a g n d 14 15 v o u t - t 1 v d d - t 1 v d d - b 1 v o u t - b 1 15 16 a g n d v r d - t 1 v g t - b v o g - 1 16 17 h1- t 1, t2 h4- t 1, t2 h3-b 1, b2 h2-b 1, b2 17 18 v s r c - 2 v o f d - t v r d - b 2 a g n d 18 19 v o u t - t 2 v d d - t 2 v d d - b 2 v o u t - b 2 19 20 a g n d v r d - t 2 v s s v o g - 2 20 21 n / c n / c n / c n / c 21 22 n / c v s s v s s n / c 22 23 n / c v s s v s s n / c 23 24 n / c n / c n / c n / c 24 25 v o g - 3 v s s v r d - b 3 a g n d 25 26 v o u t - t 3 v d d - t 3 v d d - b 3 v o u t - b 3 26 27 a g n d v r d - t 3 v o f d - b v s r c - 3 27 28 h2- t 3, t4 h3- t 3, t4 h4-b 3, b4 h1-b 3, b4 28 29 v o g - 4 v g t - t v r d - b 4 a g n d 29 30 v o u t - t 4 v d d - t 4 v d d - b 4 v o u t - b 4 30 31 a g n d v r d - t 4 v s s v s r c - 4 31 32 h1- t 3, t4 h4- t 3, t4 h3-b 3, b4 h2-b 3, b4 32 33 n / c v s s n / c a g n d 33 34 n / c n / c n / c n / c 34 35 a g n d n / c v s s n / c 35 36 og-t 3 , t4 r-t 3 , t4 r-b3, b4 og-b3, b4 36 37 v 1 x - t v 2 x - t v 3 h s - b v t g - b 37 38 v 3 x - t v s w 1 2 8 - d v 1 h s - b v 2 h s - b 38 39 v 3 a - t v s w 4 - u v 1 a - b v 2 a - b 39 40 v 3 c - t v s w 8 - u v 1 c - b v 2 c - b 40 41 v 3 d - t v s w 1 6 - u v 1 d - b v 2 d - b 41 42 v 3 e - t v s w 3 2 - u v 1 e - b v 2 e - b 42 43 v 3 f - t v s w 6 4 v 1 f - b v 2 f - b 43 44 v s s v s s v s s v s s 44 1801 mccarth y blvd., milpita s ca 95035; (8 00) 3 25-6975; fa x (40 8 ) 435- 7352; ww w . f a irchildimaging.com page 15 of 17
preliminary data sheet CCD5061 6k x 128 element tdi ? time , delay and integration sensor packag e diagram 1801 mccarth y blvd., milpita s ca 95035; (8 00) 3 25-6975; fa x (40 8 ) 435- 7352; ww w . f a irchildimaging.com page 16 of 17
preliminary data sheet CCD5061 6k x 128 element tdi ? time , delay and integration sensor co smeti c gra d i n g device grading helps to es tablish a ranking for the image qualit y t h at a c cd w ill p r ovide. blemishes are characterized as spurious pixels e x ceeding 10% of v sat w i th respect to n e ighboring elem ents. blemish content is determined in the dark, at vari ous illumination l e vels and at different o perating tempe r a t ures. wa r r a n t y fairchild imaging w a rrants that its products w ill b e free of defects in ma terial and w o rkmanship under normal use and service for one year from date of shipment. certifi c a t i o n fairchild imaging certifies that all products are car e fully inspected and tested at the fac t or y p r ior to shi p ment and w ill meet all requirements of the specific ations under w h ich it is furnished. this product is designed, m anufa c tured and distributed utiliz ing the iso 9000 :2000 b u siness management sy s t e m fairchil d ima g in g 1801 mccar t h y bl v d ., mil p itas c a 95035 (800) 3 25-69 75 o r (408 ) 433 -2500 ?2001 fairchild imaging rese rves the right to make changes to its products and/o r their specifications at an y time w i thout notice. printed in the u.s.a. 1801 mccarth y blvd., milpita s ca 95035; (8 00) 3 25-6975; fa x (40 8 ) 435- 7352; ww w . f a irchildimaging.com page 17 of 17

▲Up To Search▲

Price & Availability of CCD5061

	To Download CCD5061 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .